Power Integrity Using ADS Book

This simulation workspace utilizes schematic driven time domain simulations to design low noise power delivery networks (PDN). The design starts with a simple model of a power delivery network to verify the expected natural step response, forced sinusoidal and square wave responses. The model complexity is increased to add multiple resonances to represent the voltage regulator module (VRM), the PCB inductance with bulk capacitors, and the ceramic decoupling capacitors. An optimizer is then used to search for the maximum voltage noise or rogue wave excursion that can exist with the multiple resonances and a forced digital load pattern from a real world PDN.

The workspace has the following sections:

• How low fidelity RLC capacitor models over estimate the number of capacitors needed to reduce PDN ripple.
• How high fidelity models are measured with the 2-port shunt through method to give the best dynamic range for the data
• How to use measured data to create a high fidelity multi-element lumped model using tuning and an optimizer.

The Workspace contains two folders - "01_InductorModeling" and "02_FerriteBeadsModeling." Both the inductor and ferrite bead models use measured data to obtain the parameters. Sample measured data is available inside the folders "...\AEM_FERRITE_BEADS_wrkndatanInductorMeasuredDatan" and "...\AEM_FERRITE_BEADS_wrkndatanFerriteBeadsMeasuredDatan" Refer to [5, chapter7] for high-fidelity DC biased measurements. The ADS Optimizer is used to tunethe model parameters. A component (inductor or ferrite bead) model can be createdwith its measurement data and the procedure is explained in this chapter.

The workspace follows along with the examples in the video and has the following sections:

• A VRM Reference Design vs an Improved VRM Design that shows the goal of this workspace.
• Why it is important to have a flat PDN impedance design for the VRM
• A Voltage Mode vs Current Mode VRM simulation using state based averaged models
• VRM Error Amp Feedback Design: Shunt vs Series
• Exploring the impact of worst case fabrication tolerances on Voltage Mode vs Current Mode
• Combining a State-Based Average VRM model with a Switch Mode transient model for design exploration.

This workspace is used by Chapter 6 and Chapter 7. The state space models explained in this workspace are based on measurement results. The power integrity eco-system can be built with the measurement based models by including the PCB layout effects. The Workspace contains the following topics,

• The LM25116 with Voltage Amp Feedback (a buffered OTA)
• The Simple LM20143 with Output Transconductance Amplifier (OTA) Feedback
• Multiphase Operation with the TPS40140
• Building the Power Integrity Eco-System with VRM and PDN Models

This workspace is used by Chapter 9 and Chapter 8. The decoupling capacitor optimizations explained in this workspace are required to obtain a flat impedance profile which is essential for power integrity. The Workspace contains the following topics,

• Parallel LC resonances
• Calculating C value for flat impedance profile
• Adding PCB parasitics using the layout file in PIPro for EM simulations
• Conventional capacitor selection methods for a PDN
• DDR4 decoupling capacitor optimization

This Workspace studies various cases of anti-resonant peak formation when two capacitors are connected in parallel. It has the following sections:

• Three Cases of Antiresonances
• LC Tank Circuit
• Equal Capacitors with Positive and Negative Coupling
• Different Capacitors with Positive and Negative Coupling
• Critical Damping of Two Capacitors

The workspace contains one schematic for studying the effect of ground loop on 2-port shunt-through impedance measurements and how the common mode transformer breaks this loop. The transformer coupling coefficient T=1 breaks the ground loop. The condition T=0 is equivalent to NOT having a transformer in the loop. The Zg is the impedance of the ground loop. The IEC safety standard allows you to have a maximum of 50? in the ground loop which is utilized by some VNAs to break the ground loop. However, this is less effective than having a ground loop breaking common mode transformer or a solid state ground loop breaker. The Zg can be 1nH+0.1m?(represents a small impedance) or 1nH+50m?(allowed maximum impedance through IEC standards). The 1nH represents that the two ports of the VNAs are physically separated and will have a small inductance of the connection.

This Workspace explains with example what the die/chip sees as impedance looking into the PDN. This impedance is not same as the transfer impedance between VRM and the die/chip. The 2-port shunt-through impedance configuration is used to measure ultra-low impedance(m?s and lower) in power integrity measurements. Its connection geometry is such that both the ports are connected to the same point. The differences between the different type of port connections are explained with examples in this Workspace.