SEGGER J-Link 20-pin connector pinout: JTAG, SWD, cJTAG and SPI
Every SEGGER J-Link (except the J-Link EDU mini), the J-Trace PRO 20-pin port and every SEGGER Flasher uses the same 20-pin, 0.1" (2.54 mm) 2x10 IDC connector. This page gives the pin assignment for each interface the probe supports, the minimum wiring for SWD, and the adapters to use when your board has a smaller header.
Minimum wiring for SWD
Most Arm Cortex-M targets are debugged over SWD. You need five connections, plus SWO if you want trace output:
| Pin | Signal | Why it matters |
|---|---|---|
| 1 | VTref | Target supply reference. Sets the probe's I/O levels and tells it the target is powered. Feed it directly from target Vdd, with no series resistor. |
| 7 | SWDIO | Bidirectional SWD data. |
| 9 | SWCLK | SWD clock from the probe. |
| 15 | nRESET | Target reset, active low. Strongly recommended so the probe can halt the core out of reset. |
| 4 (or 6, 8, 10, 12) | GND | Common ground. Use more than one ground pin on long cables. |
| 13 | SWO | Optional. Serial Wire Output for printf-style trace and data logging. |
JTAG pinout
| Pin | Signal | Direction (from J-Link) | Notes |
|---|---|---|---|
| 1 | VTref | Input | Target reference voltage |
| 2 | NC | - | Not connected. Connect to Vdd or leave open |
| 3 | nTRST | Output | JTAG test reset. Keep separate from the CPU reset on pin 15 |
| 5 | TDI | Output | JTAG data into the target |
| 7 | TMS | Output | JTAG mode select. Pull up on the target |
| 9 | TCK | Output | JTAG clock |
| 11 | RTCK | Input | Return clock, for adaptive clocking on cores that need it |
| 13 | TDO | Input | JTAG data out of the target |
| 15 | nRESET | In/out | Target CPU reset, active low |
| 17 | DBGRQ | - | Not used. Leave open |
| 19 | 5V supply | Output | 5 V, up to 300 mA, overload protected |
| 4, 6, 8, 10, 12 | GND | - | Ground |
| 14, 16, 18, 20 | See note | - | See "Pins 14 to 20" below |
SWD pinout
| Pin | Signal | Direction (from J-Link) | Notes |
|---|---|---|---|
| 1 | VTref | Input | Target reference voltage |
| 2 | NC | - | Connect to Vdd or leave open |
| 3 | Not used | - | Can go to nTRST if the same header is also used for JTAG |
| 5 | Not used | - | Can go to TDI if the same header is also used for JTAG |
| 7 | SWDIO | In/out | SWD data |
| 9 | SWCLK | Output | SWD clock |
| 11 | Not used | - | Can go to RTCK if the same header is also used for JTAG |
| 13 | SWO | Input | Serial Wire Output trace (optional) |
| 15 | nRESET | In/out | Target CPU reset, active low |
| 17 | Not used | - | Unused in plain SWD; becomes VCOM Rx when VCOM is enabled (see below) |
| 19 | 5V supply | Output | 5 V, up to 300 mA |
| 4, 6, 8, 10, 12 | GND | - | Ground |
SWD with virtual COM port (VCOM)
J-Link can carry a UART alongside SWD on the same cable, so you do not need a separate USB serial adapter. The pinout is the SWD table above, with two changes:
| Pin | Signal | Direction (from J-Link) | Connect to |
|---|---|---|---|
| 5 | J-Link Tx | Output | Target UART RX |
| 17 | J-Link Rx | Input | Target UART TX |
cJTAG (2-wire JTAG) pinout
| Pin | Signal | Direction (from J-Link) | Notes |
|---|---|---|---|
| 1 | VTref | Input | Target reference voltage |
| 7 | TMSC | In/out | Serialised TMS, TDI and TDO |
| 9 | TCKC | Output | cJTAG clock |
| 15 | nRESET | In/out | Target CPU reset, active low |
| 19 | 5V supply | Output | 5 V, up to 300 mA |
| 4, 6, 8, 10, 12 | GND | - | Ground |
Pins 2, 3, 5, 11, 13 and 17 are not used in cJTAG mode.
SPI pinout (direct SPI flash programming)
| Pin | Signal | Direction (from J-Link) | Connect to |
|---|---|---|---|
| 1 | VTref | Input | Flash Vcc |
| 5 | DI | Output | Flash data in (MOSI) |
| 7 | nCS | Output | Flash chip select, active low |
| 9 | CLK | Output | Flash clock |
| 13 | DO | Input | Flash data out (MISO) |
| 15 | nRESET | In/out | Target CPU reset. Use it to hold the CPU in reset so it does not drive the SPI bus |
| 19 | 5V supply | Output | 5 V, up to 300 mA |
| 4, 6, 8, 10, 12 | GND | - | Ground |
Leave pins 2, 3, 11 and 17 open on the target side.
Pins 14 to 20
SEGGER's two published references differ on the even pins 14, 16, 18 and 20. The SEGGER knowledge base lists them as reserved and says not to assume they are grounded inside the J-Link; the J-Link interface description lists them as ground. To be safe, take your target ground from pins 4, 6, 8, 10 or 12, and leave 14 to 20 free for SEGGER's use.
Powering the target from J-Link
Pin 19 can supply 5 V at up to 300 mA, with overload and short-circuit protection. That is enough for most evaluation boards. If your target needs 3.3 V, or you want switchable power, fit the SEGGER Target Supply Adapter or the 5V Target Supply Adapter. VTref (pin 1) must still be connected to target Vdd.
When your board has a smaller header
| Target header | Use |
|---|---|
| 10-pin 0.05" (1.27 mm) Arm Cortex Debug | SEGGER 9-pin Cortex-M Adapter |
| 20-pin 0.05" Cortex Debug + ETM (with trace) | SEGGER 19-pin Cortex-M Adapter |
| 14-pin STDC14 (ST) | SEGGER STDC14 Adapter |
| No header: pads only, Tag-Connect footprint | Tag-Connect TC2050-ARM2010 adapter with a TC2050 cable |
| No header: SEGGER needle footprint | 6-pin or 10-pin Needle Adapter |
| Target at a different ground potential, or noisy power stage | JTAG Isolator or SWD Isolator |
Probes that use this connector
J-Link: BASE Classic, BASE Compact, PLUS Classic, PLUS Compact, PRO, PRO PoE, ULTRA+, WiFi.
Flasher: PRO, PRO XL, Compact, Portable PLUS, Flasher ARM.
J-Trace PRO models also have a 19-pin trace connector, covered separately.
Source
Pin assignments from SEGGER: 20-pin J-Link Connector (SEGGER knowledge base) and J-Link Interface Description. Questions about wiring a specific target: contact us.