Carte SRAM 2 Click

How Does The SRAM 2 Click Board™ Work?

The SRAM 2 Click Board™ is using nvSRAM which is ordinary SRAMs with the ability for self-sufficient, automatic backup of SRAM-data in an internal FLASH, All Read/Write operations are addressing the SRAM array only. From a user point of view, nvSRAM appears as ordinary SRAM. SRAM are fast, energy efficient and does not wear-out while R/W operations. This explains the superior speed and the unlimited R/W endurance of nvSRAM. Data transfers automatically to the non-volatile storage cells when power loss is detected or in any brown out situation (PowerStore). As long as power will be supplied within operating conditions all data stay volatile in the SRAM cells.

The SRAM 2 Click Board™ is using a standard two-wire interface (I²C) and is functional similar to serial EEPROMs or FRAM . The addressing requires a 13 bit address out of the 2-byte address of the two-wire protocol. The jumpers ADDR SEL are device address inputs to select 1 of up to 4 devices of the same type on the same I²C bus. To select one device the hard wired addresses on the 2 pins have to match with the related bits in the slave address.

This SRAM also features PowerStore operation which is a unique feature of the SONOS technology that is enabled by default on the ANV32A62A. During normal operation, the device will draw current from VCC for circuit operation and to charge a capacitor connected to the VCAP pin. This stored charge will be used by the chip to perform a single STORE operation in case of power down. If the voltage on the VCC pin drops below VSWITCH, the part will automatically disconnect the VCAP pin from VCC. A STORE operation will be initiated with power provided by the VCAP capacitor.

If a write operation is in progress all data of complete written pages are valid. Only the last incomplete written byte will be ignored. With the following Power Store execution these data become non-volatile. To reduce needless non-volatile stores, Power Store operation will be ignored unless at least one write operation has taken place since the most recent STORE cycle. The PowerStore Operation is valid for the complete memory array.

The SRAM 2 Click Board™ is powered via the mikroBUS™ 3.3V rail. However, it offers a logic voltage selection, via the VCC SEL jumper. Since the ANV32A62A memmory cannot operate with signals up to 5V, a level shifting IC is used to allow both 3.3V and 5V MCUs to be interfaced with this Click board™. The VCC SEL jumper routes either 3.3V or 5V to the voltage reference pin of the PCA9306, a dual bidirectional level shifting IC.

SPECIFICATIONS

PINOUT DIAGRAM

This table shows how the pinout of the SRAM 2 Click Board™ corresponds to the pinout on the mikroBUS™ socket (the latter shown in the two middle columns).

Notes	Pin					Pin	Notes
NC	1	AN	PWM	16	WP	Write Protect
NC	2	RST	INT	15	NC
NC	3	CS	RX	14	NC
NC	4	SCK	TX	13	NC
NC	5	MISO	SCL	12	SCL	I2C Clock
NC	6	MOSI	SDA	11	SDA	I2C Data
Power Supply	3.3V	7	3.3V	5V	10	5V	Power Supply
Ground	GND	8	GND	GND	9	GND	Ground

ONBOARD SETTINGS AND INDICATORS