nvSRAM 3 Click Board™

How Does the nvSRAM 3 Click Board™ Work?

The nvSRAM 3 Click Board™ as its foundation uses the CY14B101I, a 1-Mbit nvSRAM organized as 128K words of 8 bits each with a fully-featured real-time clock from Cypress Semiconductor. The CY14B101I specifies one million endurance cycles for cells with data retention of a minimum of 20 years, while the QuantumTrap cells provide highly reliable nonvolatile storage of data. In system power loss, data from the SRAM is automatically transferred to its nonvolatile cell using energy stored in a capacitor labelled as C2. During the Power-Up, data from the nonvolatile cell is recalled automatically in the SRAM array and available to the user. The endurance cycle consumes when data transfer happens from the SRAM cells to nonvolatile cells during the Power-Down.

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This Click board™ can be permanently powered by placing jumpers labelled as RTC-CAP or RTC-BATT. By utilizing an automatic backup, the CY14B101I uses an external battery power source from the button cell battery holder, suitable for 12mm Coin Cell batteries, when there is no power supply on its main power terminals allowing for uninterrupted operation.

The nvSRAM 3 Click Board™ communicates with MCU using standard I2C 2-Wire interface, with clock frequency up to 100kHz in the Standard, 400kHz in the Fast, 1MHz in FastPlus, and up to 3.4MHz in High-Speed Mode. The CY14B101I offers zero cycle delay write operation with infinite SRAM write endurance. It also allows the choice of the least significant bit (LSB) of its I2C slave address by positioning SMD jumpers labelled as ADDR SEL to an appropriate position marked as 0 and 1.

An additional feature of this Click board™ represents the Write Protection and Interrupt functions labelled as WP and INT routed on the PWM and INT pins of the mikroBUS™ socket. The WP pin is an active-high pin that protects the entire memory and all registers from write operations. MCU must hold the WP pin high to inhibit all the write operations. When this pin is high, all memory and register writes are prohibited, and the address counter does not increment. On the other hand, the CY14B101I can use INT pin in several ways, such as interrupt output, calibration, or a square wave, programmable to respond to the clock alarm, the watchdog timer, and the power monitor.

The STORE operation of the CY14B101I can be controlled and acknowledged via the HSB pin, routed on the RST pin of the mikroBUS™ socket. If no STORE/RECALL is in progress, the CY14B101I can use this pin to request a hardware STORE cycle. When the HSB pin is in a LOW logic state, the CY14B101I conditionally initiates a STORE operation.

The nvSRAM 3 Click Board™ can be operated only with a 3.3V logic voltage level. The board must perform appropriate logic voltage level conversion before use with MCUs with different logic levels. However, the Click board™ comes equipped with a library that contains functions and an example code that can be used, as a reference, for further development.

SPECIFICATIONS

PINOUT DIAGRAM

This table shows how the pinout of the nvSRAM 3 Click Board™ corresponds to the pinout on the mikroBUS™ socket (the latter shown in the two middle columns).

Notes	Pin	​				Pin	Notes
NC	1	AN	PWM	16	WP	Write Protect
STORE Operation Control	HSB	2	RST	INT	15	INT	Interrupt
NC	3	CS	RX	14	NC
NC	4	SCK	TX	13	NC
NC	5	MISO	SCL	12	SCL	I2C Clock
NC	6	MOSI	SDA	11	SDA	I2C Data
Power Supply	3.3V	7	3.3V	5V	10	NC
Ground	GND	8	GND	GND	9	GND	Ground

ONBOARD SETTINGS AND INDICATORS

NVSRAM 3 CLICK ELECTRICAL SPECIFICATIONS