EERAM 2 Click Board

How Does The EERAM 2 Click Board™ Work?

The EERAM 2 Click Board™ is a static RAM (SRAM) memory Click Board™ board™ with hidden EEPROM backup. This device can be treated by the user as a full symmetrical read/write SRAM with no limits on cell usage. Backup to EEPROM is handled by the device on any power disrupt, so the user can effectively view this device as an SRAM that never loses its data. The 48LM01 memory IC from Microchip, is structured as a 1024-Kbit SRAM with EEPROM backup in each memory cell. The SRAM is organized as 131,072 x 8 bits with access via the SPI serial interface. The backup EEPROM is invisible and cannot be accessed by the user independently. The 48LM01 includes circuitry that detects VCC dropping below a certain threshold, shuts its connection to the outside environment, and transfers all SRAM data to the EEPROM portion of each cell for safekeeping. When VCC returns, the circuitry automatically returns the data to the SRAM and the user's interaction with the SRAM can continue with the same data set.

When power is first applied to the Click Board™, the VCAP capacitor is charged to VCC through the 48LM01 IC. During normal SRAM operation, the capacitor remains charged and the level of system VCC is monitored by the device. If the system VCC drops below a set threshold, the device interprets this as a power-off or brown-out event. The device suspends all I/O operation, shuts off its connection with the VCC pin, and uses the saved energy in the capacitor to power the device through the VCAP pin as it transfers all SRAM data to EEPROM. On the next power-up of VCC, the data is transferred back to SRAM, the capacitor is recharged, and the SRAM operation continues.

Besides standard 4-wire SPI lines, 48LM01 has an additional HOLD pin. This pin can be used for transmission suspend to the 48LM01 while in the middle of a serial sequence without having to retransmit the entire sequence over again. It must be held high any time this function is not being used. Once the device is selected and a serial sequence is underway, the HOLD pin may be pulled low to pause further serial communication without resetting the serial sequence.

The 48LM01 is internally organized as a continuous SRAM array for both reading and writing, along with a non-volatile EEPROM array that is not directly accessible to the user, but which can be refreshed or recalled on power cycles or on software commands. The SRAM array is continuously addressable, so the entire array can be written without having to access pages.

The EERAM 2 Click Board™ uses the SPI communication interface and is designed to be operated only with a 3.3V logic level. A proper logic voltage level conversion should be performed before the Click board™ is used with MCUs with different logic levels.

SPECIFICATIONS

PINOUT DIAGRAM

This table shows how the pinout of the EERAM 2 Click Board™ corresponds to the pinout on the mikroBUS™ socket (the latter shown in the two middle columns).

Notes	Pin					Pin	Notes
NC	1	AN	PWM	16	HLD	Hold
NC	2	RST	INT	15	NC
SPI Chip Select	CS	3	CS	RX	14	NC
SPI Clock	SCK	4	SCK	TX	13	NC
SPI Data OUT	SDO	5	MISO	SCL	12	NC
SPI Data IN	SDI	6	MOSI	SDA	11	NC
Power Supply	3.3V	7	3.3V	5V	10	NC
Ground	GND	8	GND	GND	9	GND	Ground

ONBOARD SETTINGS AND INDICATORS