First released by Intel in June 2013, the Enhanced Serial Peripheral Interface (eSPI®) is designed as a replacement for the Low Pin Count (LPC) bus. eSPI®supports communication between Embedded Controller (EC), Baseboard Management Controller (BMC), Super-I/O (SIO) and Port-80 debug cards. eSPI®was vailable in the Sky Lake chipset (2015) and is available in the Kaby Lake [current] chipset. Cannonlake will support eSPI®and is slated for release the second half of 2017. Icelake is scheduled for release in 2019 and it will mark the first chipset when eSPI®becomes mandatory.
Prior to this specification, Embedded Controller (EC), Baseboard Management Controller (BMC) and Super I/O (SIO) were connected to the chipset through the Low Pin Count (LPC) bus.
PROMIRA™ Serial Platform
The PROMIRA™ Serial Platform is a powerful, fast and configurable engine for both driving serial buses and monitoring buses, non-intrusively, in real-time.
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eSPI®Analysis Application
The Total Phase eSPI®Analysis Application is the first eSPI®monitor in the industry. With this application you will be able to monitor eSPI®communication between multiple eSPI®devices:.
- Monitor communication between a master and slaves on data lines
- Support for single, dual and quad I/O
- Support for clock speeds up to 66MHz
- Monitor up to 5 channels (peripheral, virtual wire, OOB, Flash, Independent)
- Monitor up to 2 slave select lines
- Monitor 2 alert lines
- Monitor 2 reset lines
- Match triggers, hardware filters and statistics
LiveDisplay Technology
View eSPI®traffic as it is generated on the bus in true real time. Shorten debugging and development time by seeing data as they happen.