SF100 ISP Header Pin Out (2x7)
| 1 | I/O1 | I/O4 | 2 |
| 3 | I/O2 or CS2 | NC | 4 |
| 5 | VCC | GND | 6 |
| 7 | CS | CLK | 8 |
| 9 | MISO | MOSI | 10 |
| 11 | Vpp/Acc | I/O3 | 12 |
| 13 | SCL | SDA | 14 |
Intel ISP Adaptor A Pin Out (2x10)
| 1 | Key | CS0 | 2 |
| 3 | RESET | CS1 | 4 |
| 5 | GND | VCC | 6 |
| 7 | CLK | DQ2/WP | 8 |
| 9 | DQ3/HOLD | MISO | 10 |
| 11 | x | MOSI | 12 |
| 13 | x | x | 14 |
| 15 | x | x | 16 |
| 17 | x | x | 18 |
| 19 | x | x | 20 |
Signal Name Variation
Some signals have naming variations between SF100 pin out and Intel Adaptor pin out.
The following shows the signal mapping.
| SF100 connector | Intel Adaptor | ||
| Pin | Signal | Pin | Signal |
| 3 | I/O2 or CS2 | 4 | CS1 |
| 5 | VCC | 6 | VCC |
| 7 | CS | 2 | CS0 |
| 12 | I/O3 | 3 | Reset |