Acute BusFinder BF6264 Pro — 2‑in‑1 Protocol and Logic Analyser
PC‑based analyser with USB 3.0, hardware protocol decode, long‑duration logging, and 64‑channel logic capture for storage and high‑speed serial buses.
What is it?
A modular base unit that becomes a protocol analyser for eMMC, SD/SDIO, NAND, MIPI D‑PHY, UFS and more using dedicated active probes; it also runs as a 64‑channel logic analyser with timing/state capture.
Where it fits
Ideal for bring‑up, validation and failure analysis on mobile, storage and embedded designs where protocol‑aware triggers, statistics and months‑long monitoring can reveal elusive events.
Core specifications
| Capability | Value | Notes |
|---|---|---|
| Logic channels | 64 | Bus decode overlays on captured waveforms. |
| Total protocol memory | 32Gb | Hardware decode with logging to PC SSD for extended capture. |
| Timing analysis | Up to 4 GHz | High‑resolution timing for digital signals. |
| State analysis | Up to 400 MHz | State‑clocked capture for bus timing relationships. |
| Interface | USB 3.0 | Fast data link to Windows host application. |
| Operating modes | Analyser, Logger, Monitor | Real‑time, SSD logging, and trigger‑only surveillance modes. |
| Storage method | Transitional storage | Avoids decompression delays for smooth workflow. |
Available options
- eMMC 5.1 Option — Captures HS200/HS400 with CMD Queue; maps CLK/CMD/DAT[7:0] and provides protocol‑aware triggers and statistics.
- SD 3.0 (SDIO 3.0) Option — Supports SDR104 and SDIO transactions; extender cards and flying leads ease non‑intrusive tapping.
- SD 4.1 (UHS‑II) Option — Monitors UHS‑II differential links up to 1.56 Gbps per lane with link‑level events and command logging.
- NAND Flash Option — Supports ONFI 4.1 (NV‑DDR3) Mode 8 and Toggle DDR up to ~267 MHz; views ALE/CLE/WE/RE/CE/RB sequences and ECC/BBM activity.
- MIPI D‑PHY 1.2 Option — Up to 2.0 Gbps per lane, 1+4 lanes; decodes CSI‑2/DSI packets, counts ECC/CRC, and can reconstruct images for inspection.
- UFS 2.1 (M‑PHY) Option — Monitors UFS traffic over M‑PHY; useful for storage subsystems in mobile/automotive designs.
- eDP1.5 Option (eDP 1.4a) — Observes embedded DisplayPort up to 5.4 Gbps per lane with up to 4 lanes for panel and scaler bring‑up.
- SGMII Option — Tracks 10/100/1000M serial GMII links for link training, status and error conditions.
- Logic Analyser (LA) Option — Enables 64‑channel timing/state capture with bus decodes for eMMC, NAND, SD, Serial Flash (SPI NAND/SPI).
- LVDS Option — Low‑voltage differential logic measurement for clean thresholding on high‑speed differential signals.
Note Option availability and exact lane/data rates depend on the active probe and software option purchased; confirm your configuration before ordering.
Wiring quick‑start
- Identify the target bus and select the matching active probe (e.g., eMMC, SD/SDIO, MIPI D‑PHY).
- Keep tap lengths short; for high‑speed links use controlled‑impedance accessories and minimal stub length.
- Connect trigger‑out to a DSO if correlating analogue events; stacking supports MSO workflows.
- In the PC app, select the protocol, enable hardware filters to extend capture depth, and arm with a protocol‑aware trigger.
Hero/Front panel placeholder [attach product photo here].
Typical eMMC 5.1 pinout mapping
| eMMC Signal | Probe Channel | Notes |
|---|---|---|
| CLK | CLK+ | Use short, low‑inductance routing; follow probe guidance. |
| CMD | CMD | Bi‑directional; ensure proper termination/level alignment. |
| DAT0–DAT7 | DATA[0..7] | HS200/HS400 data lanes; maintain skew/channel length matching. |
| VCC/VCCQ | Sense | Voltage detect inputs help correlate supply droop to errors. |
Ready‑to‑run log parsing (CSV)
Compared to alternatives
- Prodigy PGY‑SSM focuses on SD/SDIO/eMMC with host streaming; BusFinder adds multi‑protocol options and integrated 64‑channel logic capture.
- Oscilloscope‑based D‑PHY decode aids physical‑layer and compliance; BusFinder emphasises long‑form protocol logging with hardware decode and statistics.